Advances in microprocessor technology pose new challenges for supplying power to these devices. The evolution of microprocessors began when the high-performance Pentium processor was driven by a nonstandard power supply of less than 5 V instead of drawing its power from the 5-V plane on the motherboard (Goodfellow and Weiss, 1997).
Low-voltage power management issues are becoming increasingly critical in state-of-the-art computing systems.
The current generation of high-speed CMOS processors (e.g., Alpha, Pentium, and Power PC) operates at above 300MHz with 2.5- to 3.3-V output voltage.
Future processors will be designed with even lower logic voltages of 1 to 1.5 V and increases in current demands from 13 A to 50 to 100 A (Zhang et al., 1996). Meanwhile, operating frequencies will increase to above 1 GHz. These demands, in turn, require special power supplies, voltage regulator modules (VRMs), to provide lower voltages with higher current capabilities for microprocessors.
As the speed of the processors increases, the dynamic loading of the VRMs is also significantly increased. Future microprocessors are expected to exhibit higher current slew rates of up to 5 A/ns. These slew rates represent a severe problem for the large load changes that are encountered when systems transfer from the sleep mode to the active mode and vice versa. In these cases, the parasitic impedance of the power supply connection to the load and the equivalent series resistor (ESR) and equivalent series inductor (ESL) of the capacitors have a dramatic effect on VRM voltage (Zhang et al., 1996). If this impedance is not low enough, the supply voltage may fall out of the required range during the transient period. Moreover, the total voltage tolerance will be much tighter.
Currently, the voltage tolerance is 5% (for a 3.3 V VRM output with a voltage deviation of _ 165mV). In the future, the total voltage tolerance will be 2% (for a 1.1 V VRM output with a voltage deviation requirement of only 33mV). All of these requirements pose serious design challenges and require VRMs to have very fast transient responses. Today’s VRMs are powered up from the 5-V or 12-V outputs of silver boxes that are used for supplying various parts of the system, such as the memory chips, the video cards, and some sub buses. Future VRMs will be required to provide lower voltages and higher currents with tighter voltage regulations. The traditional centralized power system, the silver box, will no longer meet the stringent requirements for VRM voltage regulation because of the distributed impedance associated with a long power bus and the parasitic ringing due to high-frequency operation.
On the other hand, with much heavier loads in the future, the bus loss becomes significant. To maintain system stability, a huge silverbox output capacitance is also needed. At the same time, to avoid the interaction between different outputs, a very large VRM input filter capacitance is required. Figure 1.2 shows the trend of computer power system architecture. In the future, a distributed power system (DPS) with a high-voltage bus, 12 V or 48 V, can be the solution for servers’ and workstations’ power systems. High-performance, high-input-voltage VRMs, however, must be developed.
To meet future requirements, a number of critical issues must be addressed. For example, advanced power devices and control technologies are needed for high-efficiency and high frequency operations. Today’s vertical power device technology cannot provide acceptable levels of conversion efficiency at a multi-megahertz level due to its high conduction and switching and gate drive losses. So the engineer needs to upgrade its power efficiency for challenging requirements of Advance Microprocessors.
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